Design

Schematic Design

The schematic is the logical board — components, nets, and the ATE conventions that make a DIB drawing readable. This is where ATE·IQ authors: schematics are generated from a prompt and the spec, imported from PDF or KiCad, and edited live — and the drawing always renders from the stored model, so it can never drift from the design it describes.

Schematic and layout are different things

ATE·IQ keeps the two concerns separate because they have different owners. The schematic — this page — is the logical design ATE·IQ generates, draws and edits. The layout — the physical copper: pads, traces, pours, drills — usually comes from your CAD flow and is imported verbatim, then checked and exported. That side is covered in PCB Layout.

Fig. 1 — One design, two concerns. The layout binding joins them on net names — which is what lets a requirement be followed onto physical copper.

Both live in the same stored model — circuit-json, the MIT-licensed open format — so there is no second representation to fall out of sync. A design can hold schematic elements alone (a drawing you generated this morning), or schematic plus copper (a vendor board you imported). Every surface reads the same model and every design records its provenance.

The ATE schematic engine

A load board schematic has a natural reading order: the DUT first, then the paths to the tester. The engine paginates that way — DUT-first, then one sheet per functional block — instead of packing everything onto one canvas.

Multi-sheet schematic view of the TMP126 load board — Fig. 2 — The TMP126 load board renders as 5 sheets: DUT · Signal Conditioning — Termination & ESD · Power & Decoupling · DC-07 DCVI · UltraPin800.

Two conventions matter on a DIB drawing, and the engine enforces both. Series terminations are drawn in signal order — tester channel → _T net → 33 Ω resistor → DUT pin — so the drawing reads the way the current flows. Kelvin connections draw both legs: force and sense as separate nets to the instrument, not a single collapsed wire.

Signal conditioning sheet — Fig. 3 — The signal-conditioning sheet: 33 Ω series-termination rows per digital pin, ESD clamps, and the ALERT pull-up.

The channel plan is authoritative

Channel flags — the tester-channel annotations on each net — are drawn from the project's saved channel plan, not from a label typed on the schematic. The drawing cannot contradict the program, because the schematic, the generated program's ChanMap, and the DIB check all read the same plan.

DC-07 DCVI instrument sheet — Fig. 4 — The DC-07 DCVI sheet: force and sense drawn as separate Kelvin legs to slot 0, flagged with their planned channels.

Where schematics come from

Source	How
Generated	The PCB Generator authors a board against your spec from a prompt — compiled offline, machine-checked, self-repaired.
Imported — PDF	Multi-page schematic PDFs: hybrid text and geometry extraction into a netlist-bearing design, for boards where the drawing is all you have.
Imported — KiCad	.kicad_sch imports directly, also picked up automatically from synced repositories.
Derived from layout	A vendor board imported via IPC-2581 / ODB++ / DSN carries its netlist — the engine renders the ATE schematic view from it.
Edited	Any of the above, modified in place — see below.

And one export of its own: the print view renders each sheet as server-side SVG for a browser save-as-PDF — the drawing pack a review meeting actually wants.

Live edits with history

Designs are editable in place, from a prompt or from the REST API. Eight operations, all pure transforms over the stored model, all gated by the validator before they persist:

Operation	Effect
add_passive	Add a resistor or capacitor onto a net.
add_part	Add a part from the reference library, with its real pins and footprint.
set_value	Change a component value.
remove_component	Remove a component and its connections.
connect_pin	Connect a pin to a net.
disconnect_pin	Disconnect a pin from a net.
relabel_net	Rename a net everywhere it appears.
rotate_component	Rotate a placed component.

Every edit journals a revision. The design header's History dropdown restores any of the newest 50 states; a single-slot Undo composes on top for the immediate step back. An edit that fails validation never reaches the stored model — and because the drawing renders from the model, a renamed net re-renders correctly on every sheet that carries it.

On the TMP126 demo

The TMP126 load board's schematic is an UltraFLEX-class DIB authored inside ATE·IQ: the DUT, 33 Ω series terminations and ESD clamps on the SPI pins, an ALERT pull-up, per-rail decoupling, Kelvin force/sense to the DC-07 DCVI, and digital I/O to UltraPin800 channels — rendered as the 5 sheets above, with every channel flag read from the saved plan.

Because the schematic's net names match the program's pin references, the test→net→copper join on the traceability dashboard resolves for every one of the 34 tests — a property the schematic engine and the saved channel plan make structural, not accidental.

Honest boundary The engine draws the stored model with ATE conventions — it is not a general-purpose schematic-capture replacement. Parts come from the reference library or from imports, and drawing a schematic never invents layout geometry: the physical copper is the layout side's concern.