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Pattern Generator

Configure a serial protocol and a transaction sequence; get cyclized IG-XL digital patterns and a live waveform. No hand-written vectors, and no gap between what the preview shows and what the pattern file contains — they are the same data structure.

01

Overview

Writing serial patterns by hand means transcribing a protocol's clocking rules into per-cycle pin states — mechanical work with mechanical failure modes. The Pattern Generator does the transcription from a declared protocol configuration, and labels every cycle with what it means.

Pattern Generator workspace with protocol config and transaction table
Fig. 1 — The workspace: protocol configuration, pin mapping, transaction table and time set, with the generated pattern alongside.

SPI covers all four CPOL/CPHA modes, MSB or LSB bit order, chip-select framing, MISO compare and masking, and a configurable frame — an ordered phase list of command, address, dummy and data phases, which is how real devices document their transactions. I2C covers START/STOP framing, 7- and 10-bit addressing, slave-ACK compare and the master NACK. Transactions support ranges and repeats; values enter as hex, decimal or binary.

02

Three layers, one source of truth

The engine is three pure layers. The middle one produces a single Vector[] — per-cycle pin states, time set, semantic label, transaction boundaries — and that array is both the pattern and the waveform. The preview cannot drift from the output because there is nothing to drift between.

1 · PROTOCOL MODEL SPI (4 CPOL/CPHA modes, phase frame) · I2C — per-cycle bit operations, labelled 2 · VECTOR ENGINE signals → DUT pins · cyclized Vector[] · repeat compression 3 · EMITTERS IG-XL ASCII (primary) · VCD · STIL · WGL one source of truth — the Vector[] IS the pattern AND the waveform; the preview cannot drift from the output three pure layers — same inputs, same vectors, every time
Fig. 2 — The three-layer engine. Emitters format the vectors; they never re-derive them.
Waveform viewer close-up: SCLK, SIO and CS over 27 cycles with drive and compare colouring, phase bands and per-bit labels
Fig. 3 — The waveform viewer on the generated DeviceIDRead pattern: solid traces are driven states, dashed blue are compare strobes (the SIO read of 0x2126), dotted is tristate. Phase bands (ADDR 0xC, DATA 0x2126) carry per-bit labels, and the viewer is zoomable per cycle. Rendered from the same Vector[] the .atp file is written from.
Pattern Generator workspace: transaction table, generate controls and the waveform panel
Fig. 4 — The viewer in place: the DEVICE_ID read transaction above, its waveform below — same screen, same vectors, no re-run.
03

Validators

Configuration errors are caught before a vector is emitted, in one shared finding format.

ValidatorWhat it catches
Bit widthA value that does not fit its declared field — a 9-bit value in an 8-bit data phase.
Pin-map completenessA protocol signal with no DUT pin assigned.
Pin conflictTwo signals mapped to the same pin.
Read compareA read transaction with no expected data to compare against.
RangeAddresses or values outside the field's representable range.
Clock rateA requested rate the cyclization cannot honour.
04

How it works

  1. Pick a project, or go standalone.

    Selecting a project loads its saved bus profile — protocol, frame phases, pin mapping, time set — plus its register map and the pattern files its generated test program already contains. Standalone mode needs only a protocol choice and a pasted pin list.

  2. Enter transactions symbolically.

    With a register map loaded, transactions are entered by register and field name rather than raw addresses, and whole test suites — reset-value reads, write/read-back — can be generated from the map in one click.

  3. Watch the waveform as you type.

    The live preview regenerates from the current configuration. Every cycle carries its semantic label — which phase, which bit — so a wrong CPOL setting is visible as a wrong waveform, not discovered at the tester.

  4. Emit.

    One generation produces all four formats: IG-XL ASCII for the tester, VCD for a waveform viewer, STIL and WGL for interchange. All are formatted from the same vectors.

05

On the TMP126 demo

Selecting the TMP126 project preloads the whole bench: the 3-wire SPI protocol with its bidirectional SIO pin, the pin mapping, the frame phases, the device's register map and the transaction sequence — and the hero pattern from the generated test program opens in the viewer automatically.

The 24 SPI patterns in the TMP126 program were not drawn in this workspace — they were derived from the test requirements by the program generator, using this same engine. The workspace lists them per project, so the pattern an engineer inspects here is byte-for-byte the pattern the program runs.

Honest boundary The generator's own validators run offline and prove internal consistency. The compile-verify step calls a real IG-XL pattern compiler when one is configured (IGXL_PATTERN_COMPILER); when none is present it reports blocked rather than pretending the pattern compiled.