Layout
PCB Layout
The layout is the physical board — pads, routed traces, pours, drills, layers. Your copper usually already exists in a CAD flow, so ATE·IQ's position is deliberate: import it verbatim, check it, bind it to the schematic, trace it, and export what the fab needs. No relayout is ever applied to a board someone already routed.
Layout and schematic are different things
The schematic is the logical design ATE·IQ authors and edits. The layout — this page — is the physical realisation, and its source of truth is usually your PCB vendor or CAD tool. ATE·IQ makes that copper a first-class, queryable, checkable artefact instead of a zip in a shared drive.
Both concerns persist in the same stored model (circuit-json), so when an analyzer reports a finding you know whether the geometry it measured came from a vendor layout or a generated draft — and the schematic and layout views can never disagree about which nets exist.
Vendor imports
A load board usually already exists somewhere — at a PCB vendor, in a legacy Allegro archive, or as a PDF nobody has the source for. The importers bring these in cold, with real copper geometry, and have been validated on real vendor boards.
| Format | Extension | Notes |
|---|---|---|
| IPC-2581 | .xml / .cvg | Full board description — components, nets, layers, copper. |
| ODB++ | .tgz | Matrix, EDA data and per-layer features to circuit-json with real copper. Validated on a 692-component rigid-flex board. |
| Specctra DSN | .dsn | KiCad, Allegro and EAGLE dialects. Pads, traces, pours, drills. |
| KiCad | .kicad_pcb | Direct board import, also picked up automatically from synced repositories. |
| Specctra SES | .ses | Round-trip: export a DSN, route it in an external tool, import the session file back onto the same design. |
Imports run from the Import menu on the design library, or automatically when a synced repository contains DSN, IPC-2581, ODB++ or KiCad files.
Copper that gets checked
Imported copper is measured, not assumed. The geometric DRC measures trace width per net class, copper-to-copper clearance and annular rings on the real geometry, each finding citing its knowledge-base rule and the measured-versus-threshold values. On top of that sit the electrical error-class gates: a same-layer different-net crossing, a trace penetrating a foreign pad, or a floating via is an error — a board that is shorted as drawn cannot pass silently. The full analyzer set is covered in Board Intelligence.
Bound to the schematic, traced to the requirement
The layout binding joins schematic nets to routed traces by net name — one resolution law shared by the viewer, the analyzers and the traceability chain. That join is what makes the layout more than a picture: select a requirement in the layout view and its nets render as an amber overlay inside the same render pass, so the highlight is exactly aligned with the copper by construction. Tester-side series-termination and Kelvin nets are included and disclosed as such.
Exports and the fabrication gate
Every export reads the canonical model. The full set, per design:
| Export | Contents | Gate |
|---|---|---|
| Gerber + Excellon | Per-layer copper plus drill files. | fab readiness |
| Fab package | One zip: copper, drills, BOM, pick-and-place, and a readiness README stating what the package contains and what it does not. | fab readiness |
| Pick-and-place | Placement CSV for assembly. | fab readiness |
| BOM | Bill of materials CSV. | — |
| KiCad project | Editable schematic and board files. | — |
| Specctra DSN | Routable netlist — round-trips back via Import SES. | — |
| IPC-2581 Rev C | Connectivity-only today. | — |
| circuit-json | The stored model itself, as <slug>.circuit.json. | — |
| Schematic PDF | Print view over server-rendered per-sheet SVG; save as PDF from the browser. | — |
The fabrication outputs sit behind a readiness gate. A schematic-only design — one with no board geometry — cannot produce Gerbers that mean anything, so the server refuses the request rather than emitting empty files, and the export menu warns before you click. A file you can download is a file a fab could use.
Working a board through
- Bring the copper in.
Import the vendor archive — IPC-2581, ODB++, DSN, KiCad or a routed SES session. The geometry lands verbatim, provenance recorded.
- Check it.
Geometric DRC measures the real copper; the electrical gates catch shorts, pad encroachment and floating vias as errors. Findings cite their rules and measured values.
- Bind and trace it.
The layout binding joins nets to traces; the traceability chain extends requirement → test → net onto physical copper, and the requirement highlight shows it.
- Export what the fab needs.
Gerbers, the one-zip fab package, BOM and pick-and-place — gated on real board geometry — plus editable KiCad, DSN and IPC-2581 for the tools downstream.
On the TMP126 demo
The TMP126 board carries routed two-layer copper: 0.25 mm signal traces with 45° mitered bends, a 1.524 mm force run necking down at the Kelvin tap, ground pour with stitch vias, and slot contact runs to the tester edge. The electrical DRC passes with zero errors and zero warnings, and because the copper's net names match the program's pin references, the requirement highlight resolves for all 34 tests.