Design
Decide which DUT pin lands on which tester channel, site by site, against the real tester configuration — and save it once. The saved plan is the program's channel contract: the generated channel map, the schematic, the board check, the IG-XL agent and the DIB checker all read that one plan, and none of them keeps a copy of its own.
Pins down the rows, sites across, and every choice drawn from the instruments the tester configuration actually contains — not a spreadsheet convention checked after the fact.
Start from the pins you already have: the spec, an imported board, an existing program's pin and channel maps, or a list typed by hand. Paste the tester's configuration and assignment becomes type-aware: a digital pin is offered digital channels, a power pin DCVI channels with force and sense.
Auto-assign fills a board's worth of blank cells with channels of the right family, and checks its own proposal against the full DIB catalogue before offering it. It fills blanks only — a channel you picked is kept exactly as you left it and taken out of the pool. Pin metadata survives save and reload: a ground pin recorded with no channel stays a ground pin with no channel, instead of being dropped as incomplete.
The saved plan is authoritative. Every surface that needs a channel reads it, so a channel chosen here is the channel everywhere:
The generated IG-XL project's channel map is emitted from the plan's saved picks, so a channel you chose lands in the program as chosen. The schematic draws each DUT pin with its planned channel. The board↔program sync reads the plan to find the board you bound to it, and reports any pin the board and the program disagree about as a finding. Ask the IG-XL agent for the channel plan or a DIB check and it answers from the same saved picks.
The plan also learns from the program. After a program is generated, the channels it needed are written back into the plan — blank cells only: a pick you made is never overwritten, and the board you bound stays bound — so from the second run on, the plan already holds what the program needs.
The 166-rule DIB checker runs offline: in the editor on the saved plan, and in the analysis hub on the workbook's own channel map sheet when one has been ingested (on the saved plan otherwise). It replaces the export-to-command-line round trip for day-to-day iteration.
Its catalogue spans the channel picture of a DIB: generic channel-token and slot checks; DC instruments and DC sources; digital channels, including the limits of their capture and source engines; AC capture; and serial and RF.
Severity is earned, not assigned by taste. Only a rule grounded in documented platform constraints, and not rated a high risk of blocking a correct board, may fail a plan — 6 of the 166 — and the catalogue refuses to build if any other rule is marked to fail. The rest warn or inform, so a finding's weight tells you how sure the checker is.
All 166 rules run on every check. A rule the plan cannot be judged on is reported as not applicable, never counted as a pass, and carries its reason — for most, the input that would switch it on. Enter the DUT's power forces and the instrument-envelope rules judge them. Per-pin roles can be proposed from the ingested spec, each proposal quoting the spec text it came from; confirming them turns on the rules that depend on them.
The saved plan is written to travel. Inbound, the board↔program sync checks an imported board's nets against the program's pins and the kind of channel each one uses. Outbound, ATE·IQ writes the plan as a first draft of the DIB in Allegro's own input grammar: a netlist for Import Logic, and a placement seed for Import Placement that puts the DUT at your template's socket centre, from the coordinates you give it.
The draft is built from the project, not from a prompt: one net per program pin, Kelvin force and sense legs plus bypass on every supply, a series leg and a test point on every signal, and a clearly labelled tester-interface placeholder whose contacts carry each net's planned channel as a property — so the channel travels inside the netlist the layout tool imports. Nothing here draws copper; routing stays with the layout engineer, in the tool that owns it.
The demonstration project's saved plan is deliberately small: one site and nine pins, eight of them on tester channels across two slots, and a ground pin recorded with no channel. It stores no tester configuration.
Measured on the demonstration project's saved channel plan.
Even a plan this small shows how the checker reports. The nine rules that apply are judged; the other 157 are set aside rather than passed; and the checker lists what would switch more of them on — a tester configuration, force limits and per-pin roles.