Verify

Board Intelligence

Every design gets the same battery of deterministic analyzers — power domains, pin match, test impact, a 166-rule DIB check, geometric and electrical DRC, and a join against production STDF history. Pure functions over the stored model: no LLM in the verdict path, same inputs, same findings, every time.

The analysis hub

One page per design collects every check. The analyzers run server-side on load, against the live stored model — there is no cached report to go stale.

Analysis hub for the TMP126 load board — Fig. 1 — The TMP126 board's analysis hub: power rails, DIB check, pin match, test impact and STDF history on one page.

Section	What it answers
Power	Rails, their sources, their loads, their bypass capacitors — with eight issue families, from a rail with no source to a load with no local decoupling.
Rails vs tester config	Does each rail's planned instrument actually exist in the parsed tester configuration, and can it deliver the rail's range?
DIB check	The 166-rule native DIB checker, run against the board and the saved channel plan.
Pin match	Board pins reconciled against the channel plan and the program's pins, tolerant of naming conventions (DUT_, _DUT, DIB_ prefixes normalise before comparison).
Test impact	Which board components each test depends on — and, reversed, which tests a component change would touch.
STDF history	Production lots joined onto this board: marginal tests named, with the board components to probe first.
ATE design rules	The applicable subset of 400+ cited ATE load-board rules, each finding carrying its source citation.
Checks	The consolidated findings collector — the same one the PCB Generator's repair loop uses — including geometric and electrical DRC.

Fig. 2 — One design fans out to the analyzers; findings come back classed by severity, each citing its rule and its measured value.

The knowledge behind the checks

The rule content is not heuristic. The DIB checker implements a catalogue of 164 rules covering channel assignment, instrument capability and board structure — a native replacement for the vendor's command-line check loop. The ATE design rules are a registry of 400+ load-board rules, each one citing its source document and carrying a confidence tag. A finding tells you where the rule came from, not just that a rule fired.

The checkers also know what a DIB is supposed to look like. Series-termination nets (the _T convention) and Kelvin force/sense pairs are recognised as deliberate DIB structure and reported as info-class disclosures — not flagged as warnings for the crime of being correct. A checker that cries wolf on every properly terminated net trains engineers to ignore it.

Geometric and electrical DRC

On boards with routed copper, the geometric DRC measures the actual geometry: trace width per net class, pad-to-trace clearance, annular ring. Each finding cites its knowledge-base rule id and reports the measured value against the threshold — 0.14 mm measured, 0.20 mm required — so the fix is quantified before anyone opens a layout tool.

A separate class of checks is electrical, and these are errors, not warnings: same-layer crossings between traces of different nets, pad encroachment, and floating vias. A board that is shorted as drawn cannot pass silently. These checks exist because a visually plausible board once carried 78 invisible crossings — plausible is not the standard; measured is.

Routed copper near the DUT after electrical DRC — Fig. 3 — The TMP126 board's copper at the DUT after routing against the electrical DRC: 45° bends, zero same-layer crossings, zero floating vias.

From yield problem to probe point

The STDF history section joins production lots onto the board. When a test trends marginal, the test-impact analysis walks from the test's pins through the board's nets to the components in the measurement path — and names them, ranked. The first question at a debug bench is what do I probe?; this section answers it from data already in the project.

Join the lots.
Ingested STDF lots join onto the board's project. Yield and per-test Cpk compute from the parsed records.
Flag the marginal test.
A test whose Cpk falls below threshold is surfaced with its number, name and trend across lots.
Walk test → pins → nets → components.
The test's attributed pins resolve through the channel plan to board nets, and the nets to the components on them.
Name the suspects.
The components in the measurement path are listed as debug suspects, ranked — the probe list before the board is on the bench.

On the TMP126 demo

On the demo board the hub reads coherently end to end. The DIB check passes 101 of 101 applicable rules. Pin match reconciles every board pin against the channel plan and the program. The electrical DRC reports zero errors on the routed copper.

The STDF join earns its place: final-test lots show test 1100 (active supply current) at Cpk 0.27, and the hub names the debug suspects — U1, R2, R9 — the components in that test's measurement path. The termination and Kelvin nets appear as info-class structure disclosures, not as noise.

Honest boundary Sections without their input data say so. No saved channel plan means the DIB check reports awaiting-data with the step that unlocks it; no ingested STDF means no history join — never an empty chart dressed as a clean one. And 101/101 means 101 applicable rules: rules whose preconditions this board does not meet are reported as not applicable, not counted as passes.